Embedded memory module design for video signal processing

Tian-Sheuan Chang*, Chein Wei Jen

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations


Two embedded memory designs are proposed and implemented for video signal processing. Complying with the features of video signal processing, concurrent line access emulates the multiport capability with single port cell hardware and little access time overhead. Layout area is 56% of two port implementation for size 2 Kb. Block access mode provides fast addressing (26% faster than conventional scheme for size 256 w×32 b). Although these two fast modes exhibit some restriction of prefer-access-order, it is no loss of generality because video signal processing algorithms possess high data parallelism and less dependency.

Original languageEnglish
Number of pages10
StatePublished - 1 Dec 1995
EventProceedings of the 1995 IEEE Workshop on VLSI Signal Processing - Osaka, Jpn
Duration: 16 Oct 199518 Oct 1995


ConferenceProceedings of the 1995 IEEE Workshop on VLSI Signal Processing
CityOsaka, Jpn

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