Embedded memory module design for video signal processing

Tian-Sheuan Chang; Chein Wei Jen

Embedded memory module design for video signal processing

Tian-Sheuan Chang^*, Chein Wei Jen

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

Two embedded memory designs are proposed and implemented for video signal processing. Complying with the features of video signal processing, concurrent line access emulates the multiport capability with single port cell hardware and little access time overhead. Layout area is 56% of two port implementation for size 2 Kb. Block access mode provides fast addressing (26% faster than conventional scheme for size 256 w×32 b). Although these two fast modes exhibit some restriction of prefer-access-order, it is no loss of generality because video signal processing algorithms possess high data parallelism and less dependency.

Original language	English
Pages	501-510
Number of pages	10
State	Published - 1 Dec 1995
Event	Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing - Osaka, Jpn Duration: 16 Oct 1995 → 18 Oct 1995

Conference

Conference	Proceedings of the 1995 IEEE Workshop on VLSI Signal Processing
City	Osaka, Jpn
Period	16/10/95 → 18/10/95

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title = "Embedded memory module design for video signal processing",

abstract = "Two embedded memory designs are proposed and implemented for video signal processing. Complying with the features of video signal processing, concurrent line access emulates the multiport capability with single port cell hardware and little access time overhead. Layout area is 56% of two port implementation for size 2 Kb. Block access mode provides fast addressing (26% faster than conventional scheme for size 256 w×32 b). Although these two fast modes exhibit some restriction of prefer-access-order, it is no loss of generality because video signal processing algorithms possess high data parallelism and less dependency.",

author = "Tian-Sheuan Chang and Jen, {Chein Wei}",

year = "1995",

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day = "1",

language = "English",

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AU - Jen, Chein Wei

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N2 - Two embedded memory designs are proposed and implemented for video signal processing. Complying with the features of video signal processing, concurrent line access emulates the multiport capability with single port cell hardware and little access time overhead. Layout area is 56% of two port implementation for size 2 Kb. Block access mode provides fast addressing (26% faster than conventional scheme for size 256 w×32 b). Although these two fast modes exhibit some restriction of prefer-access-order, it is no loss of generality because video signal processing algorithms possess high data parallelism and less dependency.

AB - Two embedded memory designs are proposed and implemented for video signal processing. Complying with the features of video signal processing, concurrent line access emulates the multiport capability with single port cell hardware and little access time overhead. Layout area is 56% of two port implementation for size 2 Kb. Block access mode provides fast addressing (26% faster than conventional scheme for size 256 w×32 b). Although these two fast modes exhibit some restriction of prefer-access-order, it is no loss of generality because video signal processing algorithms possess high data parallelism and less dependency.

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M3 - Paper

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EP - 510

Y2 - 16 October 1995 through 18 October 1995

ER -

Embedded memory module design for video signal processing

Abstract

Conference

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