Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach

Pin Su; Wei Xiang You

doi:10.1109/IEDM19573.2019.8993444

Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach

Pin Su^*, Wei Xiang You

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

Using an analytical subthreshold potential model, this paper shows that the negative-capacitance FinFET (NC-FinFET) inherently possesses a superior electrostatic integrity than the baseline FinFET. Taking into account the spacer induced distributed charges in our subthreshold model, we demonstrate that an adequate spacer design can be utilized to further enhance the NC effect and the electrostatic integrity for NC-FinFETs. This may serve as a way to extend the FinFET scaling.

Original language	English
Title of host publication	2019 IEEE International Electron Devices Meeting, IEDM 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Number of pages	4
ISBN (Electronic)	9781728140315
DOIs	https://doi.org/10.1109/IEDM19573.2019.8993444
State	Published - Dec 2019
Event	65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States Duration: 7 Dec 2019 → 11 Dec 2019

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2019-December
ISSN (Print)	0163-1918

Conference

Conference	65th Annual IEEE International Electron Devices Meeting, IEDM 2019
Country	United States
City	San Francisco
Period	7/12/19 → 11/12/19

Access to Document

10.1109/IEDM19573.2019.8993444

Fingerprint Dive into the research topics of 'Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach'. Together they form a unique fingerprint.

Cite this

Su, P., & You, W. X. (2019). Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach. In 2019 IEEE International Electron Devices Meeting, IEDM 2019 [8993444] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2019-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM19573.2019.8993444

@inproceedings{d37af1b0935049c893964e28e600cbe1,

title = "Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach",

abstract = "Using an analytical subthreshold potential model, this paper shows that the negative-capacitance FinFET (NC-FinFET) inherently possesses a superior electrostatic integrity than the baseline FinFET. Taking into account the spacer induced distributed charges in our subthreshold model, we demonstrate that an adequate spacer design can be utilized to further enhance the NC effect and the electrostatic integrity for NC-FinFETs. This may serve as a way to extend the FinFET scaling.",

author = "Pin Su and You, {Wei Xiang}",

year = "2019",

month = dec,

doi = "10.1109/IEDM19573.2019.8993444",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2019 IEEE International Electron Devices Meeting, IEDM 2019",

address = "United States",

note = "null ; Conference date: 07-12-2019 Through 11-12-2019",

}

Su, P & You, WX 2019, Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach. in 2019 IEEE International Electron Devices Meeting, IEDM 2019., 8993444, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2019-December, Institute of Electrical and Electronics Engineers Inc., 65th Annual IEEE International Electron Devices Meeting, IEDM 2019, San Francisco, United States, 7/12/19. https://doi.org/10.1109/IEDM19573.2019.8993444

Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach. / Su, Pin; You, Wei Xiang.

2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8993444 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2019-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach

AU - Su, Pin

AU - You, Wei Xiang

PY - 2019/12

Y1 - 2019/12

N2 - Using an analytical subthreshold potential model, this paper shows that the negative-capacitance FinFET (NC-FinFET) inherently possesses a superior electrostatic integrity than the baseline FinFET. Taking into account the spacer induced distributed charges in our subthreshold model, we demonstrate that an adequate spacer design can be utilized to further enhance the NC effect and the electrostatic integrity for NC-FinFETs. This may serve as a way to extend the FinFET scaling.

AB - Using an analytical subthreshold potential model, this paper shows that the negative-capacitance FinFET (NC-FinFET) inherently possesses a superior electrostatic integrity than the baseline FinFET. Taking into account the spacer induced distributed charges in our subthreshold model, we demonstrate that an adequate spacer design can be utilized to further enhance the NC effect and the electrostatic integrity for NC-FinFETs. This may serve as a way to extend the FinFET scaling.

UR - http://www.scopus.com/inward/record.url?scp=85081064181&partnerID=8YFLogxK

U2 - 10.1109/IEDM19573.2019.8993444

DO - 10.1109/IEDM19573.2019.8993444

M3 - Conference contribution

AN - SCOPUS:85081064181

T3 - Technical Digest - International Electron Devices Meeting, IEDM

BT - 2019 IEEE International Electron Devices Meeting, IEDM 2019

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 7 December 2019 through 11 December 2019

ER -

Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach

Abstract

Publication series

Conference

Access to Document

Other files and links

Cite this