Electrostatic integrity and performance enhancement for UTB InGaAs-OI MOSFET with high-k dielectric through spacer design

Vita Pi Ho Hu, Angada B. Sachid, Chang Ting Lo, Pin Su, Chen-Ming Hu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

The impact of spacer design on the electrostatic integrity (EI) and performance of Ultra-Thin-Body (UTB) InGaAs-OI MOSFETs with various high-k dielectrics are analyzed. With fixed EOT and Ioff, performance and EI degrade as gate dielectric constant (k) increases. Compared with nitride spacer, UTB InGaAs-OI MOSFET with vacuum spacer can mitigate the EI and performance degradations due to thicker physical layer of high-k dielectric. UTB InGaAs-OI MOSFET with high-k dielectric (k ≥ 18) and vacuum spacer shows larger Ion, smaller DIBL and subthreshold swing than that with nitride spacer. With fixed EOT, using gate-to-source/drain underlap can suppress the performance degradation as gate dielectric constant increases. For UTB InGaAs-OI MOSFET with underlap design, using nitride spacer may improve its gate control of channel potential and show better performance than vacuum spacer.

Original languageEnglish
Title of host publication2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479973750
DOIs
StatePublished - 3 Jun 2015
Event2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015 - Hsinchu, Taiwan
Duration: 27 Apr 201529 Apr 2015

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
Volume2015-June
ISSN (Print)1930-8868

Conference

Conference2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015
CountryTaiwan
CityHsinchu
Period27/04/1529/04/15

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    Hu, V. P. H., Sachid, A. B., Lo, C. T., Su, P., & Hu, C-M. (2015). Electrostatic integrity and performance enhancement for UTB InGaAs-OI MOSFET with high-k dielectric through spacer design. In 2015 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2015 [7117568] (International Symposium on VLSI Technology, Systems, and Applications, Proceedings; Vol. 2015-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2015.7117568