Electrostatic discharge robustness of Si nanowire field-effect transistors

Wen Liu*, Juin J. Liou, Andy Chung, Yoon Ha Jeong, Wei Chen Chen, Horng-Chih Lin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

Electrostatic discharge (ESD) performance of N-type double-gated Si nanowire (NW) thin-film transistors is investigated, for the first time, using the transmission line pulsing technique. The ESD robustness of these devices depends on the NW dimension, number of channels, plasma treatment, and layout topology. The failure currents, leakage currents, and on-state resistances are characterized, and possible ESD protection applications of these devices for future NW field-effect-transistor-based integrated circuits are also discussed.

Original languageEnglish
Pages (from-to)969-971
Number of pages3
JournalIEEE Electron Device Letters
Volume30
Issue number9
DOIs
StatePublished - 24 Jul 2009

Keywords

  • Electrostatic discharge (ESD)
  • Failure current I
  • Nanowire (NW) field-effect transistor
  • ON-state resistance

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