Electrostatic discharge robustness of Si nanowire field-effect transistors

Wen Liu; Juin J. Liou; Andy Chung; Yoon Ha Jeong; Wei Chen Chen; Horng-Chih Lin

doi:10.1109/LED.2009.2025610

Electrostatic discharge robustness of Si nanowire field-effect transistors

Wen Liu^*, Juin J. Liou, Andy Chung, Yoon Ha Jeong, Wei Chen Chen, Horng-Chih Lin

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

16 Scopus citations

Abstract

Electrostatic discharge (ESD) performance of N-type double-gated Si nanowire (NW) thin-film transistors is investigated, for the first time, using the transmission line pulsing technique. The ESD robustness of these devices depends on the NW dimension, number of channels, plasma treatment, and layout topology. The failure currents, leakage currents, and on-state resistances are characterized, and possible ESD protection applications of these devices for future NW field-effect-transistor-based integrated circuits are also discussed.

Original language	English
Pages (from-to)	969-971
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	30
Issue number	9
DOIs	https://doi.org/10.1109/LED.2009.2025610
State	Published - 24 Jul 2009

Keywords

Electrostatic discharge (ESD)
Failure current I
Nanowire (NW) field-effect transistor
ON-state resistance

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title = "Electrostatic discharge robustness of Si nanowire field-effect transistors",

abstract = "Electrostatic discharge (ESD) performance of N-type double-gated Si nanowire (NW) thin-film transistors is investigated, for the first time, using the transmission line pulsing technique. The ESD robustness of these devices depends on the NW dimension, number of channels, plasma treatment, and layout topology. The failure currents, leakage currents, and on-state resistances are characterized, and possible ESD protection applications of these devices for future NW field-effect-transistor-based integrated circuits are also discussed.",

keywords = "Electrostatic discharge (ESD), Failure current I, Nanowire (NW) field-effect transistor, ON-state resistance",

author = "Wen Liu and Liou, {Juin J.} and Andy Chung and Jeong, {Yoon Ha} and Chen, {Wei Chen} and Horng-Chih Lin",

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T1 - Electrostatic discharge robustness of Si nanowire field-effect transistors

AU - Liu, Wen

AU - Liou, Juin J.

AU - Chung, Andy

AU - Jeong, Yoon Ha

AU - Chen, Wei Chen

AU - Lin, Horng-Chih

PY - 2009/7/24

Y1 - 2009/7/24

N2 - Electrostatic discharge (ESD) performance of N-type double-gated Si nanowire (NW) thin-film transistors is investigated, for the first time, using the transmission line pulsing technique. The ESD robustness of these devices depends on the NW dimension, number of channels, plasma treatment, and layout topology. The failure currents, leakage currents, and on-state resistances are characterized, and possible ESD protection applications of these devices for future NW field-effect-transistor-based integrated circuits are also discussed.

AB - Electrostatic discharge (ESD) performance of N-type double-gated Si nanowire (NW) thin-film transistors is investigated, for the first time, using the transmission line pulsing technique. The ESD robustness of these devices depends on the NW dimension, number of channels, plasma treatment, and layout topology. The failure currents, leakage currents, and on-state resistances are characterized, and possible ESD protection applications of these devices for future NW field-effect-transistor-based integrated circuits are also discussed.

KW - Electrostatic discharge (ESD)

KW - Failure current I

KW - Nanowire (NW) field-effect transistor

KW - ON-state resistance

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DO - 10.1109/LED.2009.2025610

M3 - Article

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JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

SN - 0741-3106

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