Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology

Ming-Dou Ker*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

To provide area-efficient output ESD protection for the scaled-down CMOS VLSI. a new output ESD protection is proposed. In the new output ESD protection circuit, there are two novel devices, the PTLSCK. (PMOS-trigger lateral SCR) and the NTLSCR (NMOS-trigger lateral SCR). The PTLSCR is in parallel and merged with the output PMOS, and the NTLSCR is in parallel and merged with the output NMOS, to provide area-efficient ESD protection for CMOS output buffers. The trigger voltages of PTLSCR and NTLSCR are lowered below the breakdown voltages of the output PMOS and NMOS in the CMOS output buffer. The PTLSCR and NTLSCR are guaranteed to he turned on first before the output PMOS or NMOS are broken down by the ESD voltage. Experimental results have shown that the PTLSCR and NTLSCR can sustain over 4000 V (700 V) of the human-body-model (machine-model) ESD stresses within a very small layout area in a 0.6 μm CMOS technology with LDD and polycide processes. The noise margin of the proposed output ESD protection design is greater than 8 V (lower than -3.3 V) to avoid the undesired triggering on the NTLSCR (PTLSCR) due to the overshooting (undershooting) voltage pulse on the output pad when the IC is under normal operating conditions with 5 V VDD and 0 V VSS power supplies,

Original languageEnglish
Pages (from-to)619-639
Number of pages21
JournalMicroelectronics Reliability
Volume38
Issue number4
DOIs
StatePublished - 1 Jan 1998

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