Electrical testing structure for stacking error measurement in 3D integration

Shih Wei Lee, Shu Chiao Kuo, Kuan-Neng Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A novel electrical test structure is proposed to inspect the stacking fault in 3D integration. This approach is one nondestructive analysis of the misalignment investigation. In order to determine the misalignment of wafer/chip stacking, the metal line pattern is designed to detect the direction and quantity of stacking fault. Testing circuit diagram is proposed and simulated for efficient measurement. In addition, different types of stacking fault including translation, rotation, and run out are discussed and formulated.

Original languageEnglish
Title of host publication2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467394789
DOIs
StatePublished - 27 May 2016
EventInternational Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016 - Hsinchu, Taiwan
Duration: 25 Apr 201627 Apr 2016

Publication series

Name2016 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016

Conference

ConferenceInternational Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2016
CountryTaiwan
CityHsinchu
Period25/04/1627/04/16

Fingerprint Dive into the research topics of 'Electrical testing structure for stacking error measurement in 3D integration'. Together they form a unique fingerprint.

Cite this