Electrical performance improvement in SiO2/HfSiO high-k gate stack for advanced low power device application

M. F. Wang*, Tuo-Hung Hou, K. L. Mai, P. S. Lim, L. G. Yao, Y. Jin, S. C. Chen, M. S. Liang, W. H. Wu, S. C. Ou, M. C. Chen, T. Y. Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

A study on the impacts of varying base oxide thickness, Si composition and nitridation on HfSiO to the overall high-k gate stack performance was carried out in details. Increasing base oxide thickness from 8A to 12A was found to reduce susceptibility of charge trapping within HfSiO layer and improve drive current. Also, increasing Si composition in HfSiO layer from 50% to 75% produced a higher drive current. However, this improvement was achieved at the expense of a higher gate leakage current. The HfSiO, when subjected to N2 plasma, forms HfSiON that exhibits excellent high-k dielectric properties with low EOT, low leakage current and high driving current [1][2]. With complete understanding on the contribution from each layer, a good high-k gate stack, based on HfSiON was fabricated. Leakage current was successfully reduced to three orders lower than the conventional SiO2.

Original languageEnglish
Title of host publication2004 International Conference on Integrated Circuit Design and Technology, ICICDT
Pages283-286
Number of pages4
DOIs
StatePublished - 30 Aug 2004
Event2004 International Conference on Integrated Circuit Design and Technology, ICICDT - Austin, TX, United States
Duration: 17 May 200420 May 2004

Publication series

Name2004 International Conference on Integrated Circuit Design and Technology, ICICDT

Conference

Conference2004 International Conference on Integrated Circuit Design and Technology, ICICDT
CountryUnited States
CityAustin, TX
Period17/05/0420/05/04

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