Electrical characterization of inversion layer carrier profile in deep-submicron p-MOSFETs

Bin Yu*, Kiyotaga Imai, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticle

1 Scopus citations

Abstract

A simple electrical method is presented for the characterization of the inversion layer in p-channel MOSFETs with either p+ poly gate (surface channel, SC) or n+ poly gate (buried channel, BC). The d.c. centroid of the inversion layer profile, Xc, represents the effective thickness of the inversion layer in the SC device or the physical location of the buried channel in the BC device. For the first time, it is well demonstrated that, based on the small-signal gate-to-channel capacitance measurement, the global inversion layer hole profiles in both types of p-MOSFETs can be constructed from three elements, i.e. Xc (d.c. centroid), Xw (band diagram characteristic width) and ΔNinv (increment of net carrier area density).

Original languageEnglish
Pages (from-to)1355-1357
Number of pages3
JournalSemiconductor Science and Technology
Volume12
Issue number11
DOIs
StatePublished - 1 Nov 1997

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