This letter reports the electrical characteristics of nonuniform silicon nanowire nFETs with asymmetric source and drain widths. For electrostatic properties, reduced drain-induced barrier lowering (DIBL) is achieved in a device in which the source is wider than the drain. For carrier transport properties, higher values of surface-roughness-limited mobility (SR) are obtained in the sample with the wider drain size. Our electrostatic model shows that the concentration of lines of electric force is relaxed near the wider source edge, which results in smaller DIBL. The asymmetric SR is attributed to the channel surface morphology with (110)- and (100)-faceted surfaces.