Electrical characteristic and power consumption fluctuations of trapezoidal bulk FinFET devices and circuits induced by random line edge roughness

Chieh Yang Chen, Wen Tsung Huang, Yi-ming Li*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

In this work, we use an experimentally calibrated 3D quantum-mechanically-corrected device simulation to study different types of line edge roughness (LER) on the DC/AC and digital circuit characteristic variability of 14-nm-gate HKMG trapezoidal bulk FinFETs. By using a time-domain Gaussian noise function as the LER-profile generator, we compare four types of LER: fin-LER inclusive of resist-LER and spacer-LER, sidewall-LER, and gate-LER for the trapezoidal bulk FinFETs. The resist-LER is most influential on characteristic fluctuation. For the same type, spacer-LER has at least 85 % improvement on σVth compared with resist-LER. As for the digital circuit characteristic, the rectangle-shape bulk FinFET has larger timing fluctuation.

Original languageEnglish
Title of host publicationProceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
PublisherIEEE Computer Society
Pages61-64
Number of pages4
ISBN (Electronic)9781479975815
DOIs
StatePublished - 13 Apr 2015
Event16th International Symposium on Quality Electronic Design, ISQED 2015 - Santa Clara, United States
Duration: 2 Mar 20154 Mar 2015

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2015-April
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference16th International Symposium on Quality Electronic Design, ISQED 2015
CountryUnited States
CitySanta Clara
Period2/03/154/03/15

Keywords

  • digital circuit
  • fin-
  • gateLER
  • Line edge roughness
  • resist-
  • sidewall-
  • spacer-
  • trapezoidal bulk FinFET

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