Electrical and reliability investigation of Cu TSVs with low-temperature Cu/Sn and BCB hybrid bond scheme

Yao Jen Chang*, Cheng Ta Ko, Kuan-Neng Chen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

21 Scopus citations

Abstract

A wafer-level 3-D integration scheme using Cu through-silicon vias (TSVs) and fine-pitch Cu/Sn-BCB hybrid bonding was developed and investigated with electrical characterization and reliability assessment. The hybrid bonding could be achieved below 250 ° C. Low Kelvin resistance and stable daisy chain resistance were achieved in 5-and 10-μ m TSV test structures across the whole wafer. Without obvious deterioration in reliability test results, the integrated Cu TSV and hybrid bond scheme can be potentially designed for 3-D integration applications.

Original languageEnglish
Article number6373692
Pages (from-to)102-104
Number of pages3
JournalIEEE Electron Device Letters
Volume34
Issue number1
DOIs
StatePublished - 1 Jan 2013

Keywords

  • 3-D integration
  • Hybrid bonding
  • through-silicon via (TSV)

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