Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-κ Eu 2O 3 gate dielectrics

Li Chen Yen*, Chia Wei Hu, Tsung Yu Chiang, Tien-Sheng Chao, Tung Ming Pan

*Corresponding author for this work

Research output: Contribution to journalArticle

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Abstract

In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu 2O 3 gate dielectric. High-κ Eu 2O 3 LTPS-TFT annealed at 500 °C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm 2/V-s, a small subthreshold swing of 142 mV/decade, and a high I on/I off current ratio of 1.34 × 10 7. These significant improvements are attributed to the high gate-capacitance density due to the adequate quality of Eu 2O 3 gate dielectric with small interfacial layer of effective oxide thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu 2O 3 LTPS-TFT device.

Original languageEnglish
Article number173509
JournalApplied Physics Letters
Volume100
Issue number17
DOIs
StatePublished - 23 Apr 2012

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