Efficient two-layered cycle-accurate modeling technique for processor family with same instruction set architecture

Chien De Chiang*, Juinn-Dar Huang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper, we propose a new processor modeling technique that partitions a cycle-accurate model into two layers, an inner functional kernel and an outer timing shell. The kernel is an untimed but high-speed instruction set simulator (ISS) and is suitable for software development; while the timing shell provides additional timing details for cycle-accurate hardware behavior. When a new processor member is added to the family, it demands only a new timing shell because the kernel is identical to that of its ancestors sharing the same instruction set architecture (ISA). It not only helps ensure functional consistency but significantly reduces the model development time. We take two processors with a same ISA, an ARM7-like one and an ARM9-like one, as our modeling examples to demonstrate the feasibility of the proposed technique. Finally, the experimental results show that, on average our two-layered cycle-accurate model is about 30 times faster than the RTL model in simulation.

Original languageEnglish
Title of host publication2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages235-238
Number of pages4
DOIs
StatePublished - 1 Dec 2009
Event2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan
Duration: 28 Apr 200930 Apr 2009

Publication series

Name2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Conference

Conference2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
CountryTaiwan
CityHsinchu
Period28/04/0930/04/09

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