In this paper, we focus on the simulation techniques in order to reduce the space and time requirements for simulating large caches. First, we propose a space sampling technique to perform trace reduction for time and space. Our approach is to perform stratified sampling based on an index of locality. Our results show that the technique can provide accurate estimate of performance metric using only a small portion of trace references. Alternatively we also propose a time sampling approach, which performs sampling on loop iterations and requires that references between inter-loop intervals be fully simulated. We show that the time sampling technique may give representative performance results for the entire loop execution. Depending on different workloads, the approach has been shown to be very effective in reducing simulation time at the cost of small estimate errors.
|Number of pages||10|
|Journal||Proceedings of the IEEE Annual Simulation Symposium|
|State||Published - 1 Jan 1996|
|Event||Proceedings of the 1996 29th Annual Simulation Symposium - New Orleans, LA, USA|
Duration: 8 Apr 1996 → 11 Apr 1996