A new analytic timing model for characteristic waveforms of CMOS logic gates is proposed. In this model, the quasi-linear equivalent circuit of a gate is formed, and its effective dominate pole is found using the dominate-pole-dominate-zero (DPDZ) method. From the effective dominate pole, analytic equations for the rise time, the fall time, or the delay time of the gate can be derived. The new model has been applied to Si-gate CMOS inverters, multi-input NOR gates and multi-input NAND gates. Their characteristic-waveform timing equations have been derived and shown to be consistent with the computer timing simulation results. Therefore, this timing model can be used to perform timing analysis and timing synthesis efficiently and quickly.
|Number of pages||5|
|State||Published - 1 Dec 1984|