Efficient techniques in the sizing and constrained optimisation of CMOS combinational logic circuits

J. S. Hwang*, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

Two techniques are proposed which enhance the optimisation efficiency of CMOS combinational logic circuits. One uses transition times (rise and fall times) of each gate as variables of the optimisation process. The other technique uses the optimal characteristic waveform synthesising method (OCWSM) to obtain the initial guess for the optimisation process. The optimisation process, with these two techniques, can perform sizing and optimisation for circuits with a smaller fixed-delay specification than other sizing and optimisation algorithms. The circuits sized using the proposed algorithm have shown a smaller power dissipation, especially when the delay specification is small. The CPU time consumed is reasonable. High-speed low-power circuits are thus more realisable using the proposed algorithm.

Original languageEnglish
Pages (from-to)154-164
Number of pages11
JournalIEE Proceedings E: Computers and Digital Techniques
Volume138
Issue number3
DOIs
StatePublished - 1 Jan 1991

Fingerprint Dive into the research topics of 'Efficient techniques in the sizing and constrained optimisation of CMOS combinational logic circuits'. Together they form a unique fingerprint.

Cite this