Efficient systolic architectures for 1-D and 2-D DLMS adaptive digital filters

Lan-Da Van*, Wu Shiung Feng

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

10 Scopus citations

Abstract

In this paper, we propose two efficient systolic architectures for 1-D and 2-D Delay Least-Mean-Square (DLMS) adaptive digital filters. Using our developed architectures, higher convergence rate and Signal-to-Noise Ratio (SNR) than those of the conventional DLMS structure can be obtained without sacrificing the properties of the systolic architecture. Furthermore, the adaptive digital filters operate at the highest throughout due to the new tree-systolic processing element. Besides, based on our proposed optimized rule, one can easily design N th tap and window size N × N systolic adaptive digital filters with the compromise of minimum delay and high regularity under the constraint of the maximum number of tap-connections of the feedback signal.

Original languageEnglish
Pages399-402
Number of pages4
DOIs
StatePublished - 1 Dec 2000
Event2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems - Tianjin, China
Duration: 4 Dec 20006 Dec 2000

Conference

Conference2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems
CountryChina
CityTianjin
Period4/12/006/12/00

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