Efficient power-analysis-resistant dual-field elliptic curve cryptographic processor using heterogeneous dual-processing-element architecture

Jen Wei Lee, Szu Chi Chung, Hsie-Chia Chang, Chen-Yi Lee

Research output: Contribution to journalArticle

42 Scopus citations

Abstract

Elliptic curve cryptography (ECC) for portable applications is in high demand to ensure secure information exchange over wireless channels. Because of the high computational complexity of ECC functions, dedicated hardware architecture is essential to provide sufficient ECC performance. Besides, crypto-ICs are vulnerable to side-channel information leakage because the private key can be revealed via power-analysis attacks. In this paper, a new heterogeneous dual-processing-element (dual-PE) architecture and a priority-oriented scheduling of right-to-left double-and-add-always EC scalar multiplication (ECSM) with randomized processing technique are proposed to achieve a power-analysis-resistant dual-field ECC (DF-ECC) processor. For this dual-PE design, a memory hierarchy with local memory synchronization scheme is also exploited to improve data bandwidth. Fabricated in a 90-nm CMOS technology, a 0.4- mm2 160-b DF-ECC chip can achieve 0.34/0.29 ms 11.7/9.3 μ J for one GF (p) GF 2 ECSM. Compared to other related works, our approach is advantageous not only in hardware efficiency but also in protection against power-analysis attacks.

Original languageEnglish
Article number6459050
Pages (from-to)49-61
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume22
Issue number1
DOIs
StatePublished - 1 Jan 2014

Keywords

  • Dual fields
  • elliptic curve cryptography (ECC)
  • heterogeneous processing-element architecture
  • parallel computations
  • power-analysis attacks

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