Efficient Physical Timing Models for CMOS AND-OR-Inverter and OR-AND-Inverter Gates and Their Applications

Chung-Yu Wu, Ming Chuen Shiau

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

Efficient physical timing models for complex CMOS AND-OR-Inverter (AOI) and OR-AND-Inverter (OAI) gates have been successfully developed. Through extensive comparisons with SPICE simulation results, the developed models have shown a maximum error of 30% for long-channel and small-geometry CMOS AOI/OAI gates with wide ranges of channel dimensions, capacitive loads, logic input patterns, circuit configurations, device parameter variations, and non-characteristic waveform input excitations. The error can be further reduced to 16% with commonly used device dimensions. The developed timing models are successfully applied to the autosizing of CMOS AOI/ OAI gates. The results show a good accuracy and a reasonable CPU time consumption.

Original languageEnglish
Pages (from-to)1002-1009
Number of pages8
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume9
Issue number9
DOIs
StatePublished - 1 Jan 1990

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