Efficient parallel adder based design for one-dimensional discrete cosine transform

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The author proposes an efficient parallel adder based design for the one-dimensional (1-D) discrete cosine transform (DCT). A new algorithm is developed that exploits the merits of cyclic convolution to facilitate the realization of a 1-D any-length DCT using parallel adders. Based on this algorithm, the proposed design possesses the advantages of low hardware cost, low input/output (I/O) cost, high computing speed, and high flexibility in transform length. Considering an example using 16-bit coefficients, the proposed design can save about 58% and 80% of the gate area, as compared with the distributed arithmetic (DA)-based designs, for the 64 and 128 transform lengths, respectively.

Original languageEnglish
Pages (from-to)276-282
Number of pages7
JournalIEE Proceedings: Circuits, Devices and Systems
Issue number5
StatePublished - 1 Oct 2000

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