Efficient memory architecture for motion estimation processor design

Eddie G. Tzeng; Chen-Yi Lee

doi:10.1109/ISCAS.1995.521616

Efficient memory architecture for motion estimation processor design

Eddie G. Tzeng^*, Chen-Yi Lee

^*Corresponding author for this work

National Chiao Tung University

Research output: Contribution to journal › Conference article › peer-review

6 Scopus citations

Abstract

This paper presents a novel memory architecture for motion estimation processor design. By means of conditional selection strategy, data items which can be reused are stored in memory banks and arranged in a snake-like way. Both integer and half pixel motion vectors can be obtained by the proposed architecture and an array processor, where memory bandwidth can be minimized and hence I/O pin-count can be reduced a lot. The proposed architecture is then demonstrated by a test chip, whose hardware efficiency of processor elements is 100% when integer motion vector is demanded.

Original language	English
Pages (from-to)	712-715
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
DOIs	https://doi.org/10.1109/ISCAS.1995.521616
State	Published - 1 Jan 1995
Event	Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA Duration: 30 Apr 1995 → 3 May 1995

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abstract = "This paper presents a novel memory architecture for motion estimation processor design. By means of conditional selection strategy, data items which can be reused are stored in memory banks and arranged in a snake-like way. Both integer and half pixel motion vectors can be obtained by the proposed architecture and an array processor, where memory bandwidth can be minimized and hence I/O pin-count can be reduced a lot. The proposed architecture is then demonstrated by a test chip, whose hardware efficiency of processor elements is 100% when integer motion vector is demanded.",

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AB - This paper presents a novel memory architecture for motion estimation processor design. By means of conditional selection strategy, data items which can be reused are stored in memory banks and arranged in a snake-like way. Both integer and half pixel motion vectors can be obtained by the proposed architecture and an array processor, where memory bandwidth can be minimized and hence I/O pin-count can be reduced a lot. The proposed architecture is then demonstrated by a test chip, whose hardware efficiency of processor elements is 100% when integer motion vector is demanded.

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M3 - Conference article

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JF - Proceedings - IEEE International Symposium on Circuits and Systems

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Y2 - 30 April 1995 through 3 May 1995

ER -

Efficient memory architecture for motion estimation processor design

Abstract

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