Efficient memory architecture for motion estimation processor design

Eddie G. Tzeng*, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

6 Scopus citations

Abstract

This paper presents a novel memory architecture for motion estimation processor design. By means of conditional selection strategy, data items which can be reused are stored in memory banks and arranged in a snake-like way. Both integer and half pixel motion vectors can be obtained by the proposed architecture and an array processor, where memory bandwidth can be minimized and hence I/O pin-count can be reduced a lot. The proposed architecture is then demonstrated by a test chip, whose hardware efficiency of processor elements is 100% when integer motion vector is demanded.

Original languageEnglish
Pages (from-to)712-715
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume1
DOIs
StatePublished - 1 Jan 1995
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: 30 Apr 19953 May 1995

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