Efficient layout style of CMOS output buffer to improve driving capability of low-voltage submicron CMOS IC's

Ming-Dou Ker*, Chung-Yu Wu, Tao Cheng, Hun Hsien Chang, Michael J.N. Wu, T. L. Yu

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

A novel square-type layout style is proposed to efficiently implement CMOS output buffer with larger W/L ratio into a smaller silicon layout area than that of conventional finger-type layout style. Using this proposed layout style, the driving capability of CMOS output buffer in low-voltage submicron CMOS IC's can be effectively improved without increasing more layout area.

Original languageEnglish
Pages193-195
Number of pages3
StatePublished - 1 Dec 1995
EventProceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology - Beijing, China
Duration: 24 Oct 199528 Oct 1995

Conference

ConferenceProceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology
CityBeijing, China
Period24/10/9528/10/95

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    Ker, M-D., Wu, C-Y., Cheng, T., Chang, H. H., Wu, M. J. N., & Yu, T. L. (1995). Efficient layout style of CMOS output buffer to improve driving capability of low-voltage submicron CMOS IC's. 193-195. Paper presented at Proceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology, Beijing, China, .