Efficient inter-layer prediction hardware design with extended spatial scalability for H.264/AVC scalable extension

Yu Chen Chen; Gwo Long Li; Tian-Sheuan Chang

doi:10.1109/ISCAS.2010.5537497

Efficient inter-layer prediction hardware design with extended spatial scalability for H.264/AVC scalable extension

Yu Chen Chen^*, Gwo Long Li, Tian-Sheuan Chang

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

To support inter-layer prediction with arbitrary frame resolution ratio between successive spatial layers, the scalable video coding (SVC) adopts the mechanism of extended spatial scalability (ESS) to achieve it but with noticeable hardware implementation complexity due to the numerous multiplication operations. Therefore, this paper proposes a hardware efficient inter-layer prediction architecture design with ESS by means of accumulator approach. In addition, an area efficient inter-layer interpolator architecture and simplified transform block identification scheme are also proposed to further reduce hardware costs. Simulation results demonstrate that our proposed architecture can significantly save gate count when compared to direct implementation approach.

Original language	English
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	665-668
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537497
State	Published - 31 Aug 2010
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: 30 May 2010 → 2 Jun 2010

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Conference

Conference	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country	France
City	Paris
Period	30/05/10 → 2/06/10

Access to Document

10.1109/ISCAS.2010.5537497

Link to publication in Scopus

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Chen, Y. C., Li, G. L., & Chang, T-S. (2010). Efficient inter-layer prediction hardware design with extended spatial scalability for H.264/AVC scalable extension. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 665-668). [5537497] (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537497

Chen, Yu Chen ; Li, Gwo Long ; Chang, Tian-Sheuan. / Efficient inter-layer prediction hardware design with extended spatial scalability for H.264/AVC scalable extension. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. pp. 665-668 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

@inproceedings{6f92a5baf1e04750893d9dd5b122fefa,

title = "Efficient inter-layer prediction hardware design with extended spatial scalability for H.264/AVC scalable extension",

abstract = "To support inter-layer prediction with arbitrary frame resolution ratio between successive spatial layers, the scalable video coding (SVC) adopts the mechanism of extended spatial scalability (ESS) to achieve it but with noticeable hardware implementation complexity due to the numerous multiplication operations. Therefore, this paper proposes a hardware efficient inter-layer prediction architecture design with ESS by means of accumulator approach. In addition, an area efficient inter-layer interpolator architecture and simplified transform block identification scheme are also proposed to further reduce hardware costs. Simulation results demonstrate that our proposed architecture can significantly save gate count when compared to direct implementation approach.",

author = "Chen, {Yu Chen} and Li, {Gwo Long} and Tian-Sheuan Chang",

year = "2010",

month = aug,

day = "31",

doi = "10.1109/ISCAS.2010.5537497",

language = "English",

isbn = "9781424453085",

series = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems",

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booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems",

note = "null ; Conference date: 30-05-2010 Through 02-06-2010",

}

Chen, YC, Li, GL & Chang, T-S 2010, Efficient inter-layer prediction hardware design with extended spatial scalability for H.264/AVC scalable extension. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537497, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 665-668, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 30/05/10. https://doi.org/10.1109/ISCAS.2010.5537497

Efficient inter-layer prediction hardware design with extended spatial scalability for H.264/AVC scalable extension. / Chen, Yu Chen; Li, Gwo Long; Chang, Tian-Sheuan.

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 665-668 5537497 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - To support inter-layer prediction with arbitrary frame resolution ratio between successive spatial layers, the scalable video coding (SVC) adopts the mechanism of extended spatial scalability (ESS) to achieve it but with noticeable hardware implementation complexity due to the numerous multiplication operations. Therefore, this paper proposes a hardware efficient inter-layer prediction architecture design with ESS by means of accumulator approach. In addition, an area efficient inter-layer interpolator architecture and simplified transform block identification scheme are also proposed to further reduce hardware costs. Simulation results demonstrate that our proposed architecture can significantly save gate count when compared to direct implementation approach.

AB - To support inter-layer prediction with arbitrary frame resolution ratio between successive spatial layers, the scalable video coding (SVC) adopts the mechanism of extended spatial scalability (ESS) to achieve it but with noticeable hardware implementation complexity due to the numerous multiplication operations. Therefore, this paper proposes a hardware efficient inter-layer prediction architecture design with ESS by means of accumulator approach. In addition, an area efficient inter-layer interpolator architecture and simplified transform block identification scheme are also proposed to further reduce hardware costs. Simulation results demonstrate that our proposed architecture can significantly save gate count when compared to direct implementation approach.

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Chen YC, Li GL, Chang T-S. Efficient inter-layer prediction hardware design with extended spatial scalability for H.264/AVC scalable extension. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 665-668. 5537497. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537497