Efficient generation of pre-silicon MOS model parameters for early circuit design

Michael Orshansky, Judy An, Chun Jiang, Bill Liu, Concetta Riccobene, Chen-Ming Hu

Research output: Contribution to journalArticle

11 Scopus citations


The technology development cycle continues to shrink, which very often requires evaluation of circuit design and technology choices using circuit simulators at the time when no real silicon is available. In this paper, we present an efficient methodology for generating pre-silicon device models for advanced CMOS processes. The methodology allows accurate prediction of the full MOS I-V characteristics for the future technologies combining a constraint back-propagation algorithm based upon a few critical specifications, physical models for the advanced device phenomena, and the empirical data from devices of an existing technology. The methodology has been tested on two CMOS production technologies. Good prediction results are achieved: for nMOS the rms error is 1%-2%, for pMOS it is 2%-4%.

Original languageEnglish
Pages (from-to)156-159
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Issue number1
StatePublished - 1 Jan 2001

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