Efficient designs of unified 2's complement division and square-root algorithm and architecture

Sau-Gee Chen*, Chieh Chih Li

*Corresponding author for this work

Research output: Contribution to conferencePaper

1 Scopus citations

Abstract

Efficient unified 2's complement division and square-root algorithm, and their architectures are proposed in this work. The designs are high speed, small area and high compatibility. The architectures provide bit-level pipelined operation, as well as parallel remainder iteration and its sign detection operations. A simplified signed-digit addition (SDA) scheme without carry-propagation delay is adopted. As such, their cycle time is minimized down to a carry-save addition time. Moreover, a fast deposition scheme of 2's complement (TC) into the sign-magnitude (SM) architecture is developed, which incurs no time penalty. A fast on-line algorithm for number conversion from SM results to TC output is also devised. The algorithm performs faster than the known on-line conversion algorithms. Most importantly, the unified divider/square-rooter have more regular geometry than the known designs, and accordingly suitable for VLSI implementation.

Original languageEnglish
Pages943-947
Number of pages5
StatePublished - 1 Jan 1995
EventProceedings of the 1994 IEEE Region 10's 9th Annual International Conference (TENCON'94). Part 1 (of 2) - Singapore, Singapore
Duration: 22 Aug 199426 Aug 1994

Conference

ConferenceProceedings of the 1994 IEEE Region 10's 9th Annual International Conference (TENCON'94). Part 1 (of 2)
CitySingapore, Singapore
Period22/08/9426/08/94

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    Chen, S-G., & Li, C. C. (1995). Efficient designs of unified 2's complement division and square-root algorithm and architecture. 943-947. Paper presented at Proceedings of the 1994 IEEE Region 10's 9th Annual International Conference (TENCON'94). Part 1 (of 2), Singapore, Singapore, .