Efficient designs of multiported memory on FPGA

Bo-Cheng Lai*, Jiun Liang Lin

*Corresponding author for this work

Research output: Contribution to journalArticle

11 Scopus citations

Abstract

The utilization of block RAMs (BRAMs) is a critical performance factor for multiported memory designs on field-programmable gate arrays (FPGAs). Not only does the excessive demand on BRAMs block the usage of BRAMs from other parts of a design, but the complex routing between BRAMs and logic also limits the operating frequency. This paper first introduces a brand new perspective and a more efficient way of using a conventional two reads one write (2R1W) memory as a 2R1W/4R memory. By exploiting the 2R1W/4R as the building block, this paper introduces a hierarchical design of 4R1W memory that requires 25% fewer BRAMs than the previous approach of duplicating the 2R1W module. Memories with more read/write ports can be extended from the proposed 2R1W/4R memory and the hierarchical 4R1W memory. Compared with previous xor-based and live value table-based approaches, the proposed designs can, respectively, reduce up to 53% and 69% of BRAM usage for 4R2W memory designs with 8K-depth. For complex multiported designs, the proposed BRAM-efficient approaches can achieve higher clock frequencies by alleviating the complex routing in an FPGA. For 4R3W memory with 8K-depth, the proposed design can save 53% of BRAMs and enhance the operating frequency by 20%.

Original languageEnglish
Article number7486977
Pages (from-to)139-150
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume25
Issue number1
DOIs
StatePublished - 1 Jan 2017

Keywords

  • Block RAM (BRAM)
  • field-programmable gate array (FPGA)
  • multiported memory
  • performance

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