In this paper, we propose a new CORDIC algorithm and architectures which can generate close-to-optimum rotation sequences easily with small lookup table sizes. This new design is particularly suitable for the applications of adjustable-length FFT. In all, the required number of shift-and-add operations for micro-rotations and scale-factor compensations is only n/2, where n is the output precision. For design verification, we synthesized both serial and pipelined architectures, by using Synopsys Design Complier based on UMC 0.18 μm, lP6M CMOS technology. The synthesized 16-bit pipelined FFT PE runs at 222MHz, with a total gate count of 89263 and a low-power consumption of 26.75 mW. It meets the FFT speed requirements of most OFDM-based communication systems, including DAB, DVB, 802.16 and VDSL. Compared with a conventional multiplier-based FFT PE and the existing CORDIC-based FFT PE's, the proposed designs has better performances in terms of area, speed and power consumption.