Efficient Bit-Level Systolic Array Implementation of Fir and Iir Digital Filters

Chin Liang Wang*, Che Ho Wei, Sin-Horng Chen

*Corresponding author for this work

Research output: Contribution to journalArticle

14 Scopus citations

Abstract

highspeed digital filters are important for Realtime digital signal processing applications. In this paper, we present some new bit-level systolic architectures based on a new inner product computation scheme for finite impulse response (FIR) and infinite impulse response (IIR) digital filterings. The FIR filter structure is optimized in the sense that, for a given clock rate, both the utilization efficiency and average throughput are maximized. The IIR filter structure has approximately the same utilization efficiency and throughput rate as previous related techniques for processing a single data stream (channel), but it allows two data streams to be processed concurrently to double the performance. This feature makes the new IIR system attractive for use in applications where multiple filtering and particularly bandpass analysis are required.

Original languageEnglish
Pages (from-to)484-493
Number of pages10
JournalIEEE Journal on Selected Areas in Communications
Volume6
Issue number3
DOIs
StatePublished - 1 Jan 1988

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