Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow

Lun Chun Wei*, Hung-Ming Chen, Li Da Huang, Sarah Songjie Xu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

As VLSI design complexity is continuously increasing, the yield loss due to via failure becomes more significant. Adding a redundant via adjacent to each single via is a well-known and highly recommended method to reduce yield loss due to via failure. In this paper, we develop a network-flow-based algorithm in post-layout stage for the redundant via insertion problem. With our novel and efficient approach, we can obtain optimal redundant via insertion solution in improving the manufacturing yield, with minimal fixup if necessary. Moreover, our approach is parallel-processing-friendly and effective in ECO incremental solution due to the nature of network-flow models.

Original languageEnglish
Title of host publicationGLSVLSI 2008
Subtitle of host publicationProceedings of the 2008 ACM Great Lakes Symposium on VLSI
Pages359-362
Number of pages4
DOIs
StatePublished - 1 Dec 2008
EventGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL, United States
Duration: 4 Mar 20086 Mar 2008

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

ConferenceGLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008
CountryUnited States
CityOrlando, FL
Period4/03/086/03/08

Keywords

  • Network flow
  • Redundant via insertion
  • Relaxation

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