Effects of spacer and single-charge trap on voltage transfer characteristics of gate-all-around silicon nanowire CMOS devices and circuits

Sekhar Reddy Kola, Yiming Li*, Narasimhulu Thoti

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We report the effects of the spacer and the single-charge trap (SCT) on the voltage transfer characteristics of cylindrical-shape gate-all-around (GAA) silicon (Si) nanowire (NW) metal-oxide-semiconductor field effect transistor (MOSFETs). We explore the impact of low-x spacer, high-x spacer, and dual spacer (DS) on electrical characteristics of the GAA Si NW MOSFET with a gate length of 10 nm. Compared with the nominal device (i.e., the device without spacer), the device with DS possesses 68.8% reduction on the normalized off-current and 29.4% increase on the normalized on-current for n- and p-type devices. Similarly, 21.1% and 3.38% improvements on the normalized high and low noise margins can be achieved for the GAA Si NW complementary metal-oxide-semiconductor (CMOS) circuit. Notably, the voltage transfer characteristics induced by the acceptor- and donor-type SCT for the CMOS circuit with DS possesses 2.64% and 3.82% enhancements for the normalized high and low noise margins compared with the nominal one.

Original languageEnglish
Title of host publicationNANO 2020 - 20th IEEE International Conference on Nanotechnology, Proceedings
PublisherIEEE Computer Society
Pages217-220
Number of pages4
ISBN (Electronic)9781728182643
DOIs
StatePublished - Jul 2020
Event20th IEEE International Conference on Nanotechnology, NANO 2020 - Virtual, Online, Canada
Duration: 29 Jul 202031 Jul 2020

Publication series

NameProceedings of the IEEE Conference on Nanotechnology
Volume2020-July
ISSN (Print)1944-9399
ISSN (Electronic)1944-9380

Conference

Conference20th IEEE International Conference on Nanotechnology, NANO 2020
CountryCanada
CityVirtual, Online
Period29/07/2031/07/20

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