Effects of Hot Carrier Induced Interface State Generation in Submicron LDD MOSFET’ s

Ta-Hui Wang, Chimoon Huang, P. C. Chou, Steve S. Chung, Tse En Chang

Research output: Contribution to journalArticle

27 Scopus citations

Abstract

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6µm LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at Vg ≃ 0.5Vdin a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states.

Original languageEnglish
Pages (from-to)1618-1622
Number of pages5
JournalIEEE Transactions on Electron Devices
Volume41
Issue number9
DOIs
StatePublished - 1 Jan 1994

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