Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Po Jung Sung, Chun Jung Su, Shih Hsuan Lo, Fu Kuo Hsueh, Darsen D. Lu, Yao Jen Lee*, Tien Sheng Chao

*Corresponding author for this work

Research output: Contribution to journalArticle

Abstract

In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with ID change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of Id. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various VD from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.

Original languageEnglish
Article number9063644
Pages (from-to)474-480
Number of pages7
JournalIEEE Journal of the Electron Devices Society
Volume8
DOIs
StatePublished - 1 Jan 2020

Keywords

  • FeFET
  • ferroelectric
  • forming gas annealing (FGA)
  • HfZrO
  • steep slop

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