The effect of ultrathin Si passivation layer on Ge MOS characteristics with La2O3 gate dielectric has been examined. Hysteresis on C-V curve was significantly reduced by inserting a Si passivation with thickness of over 1 nm due to suppression of Ge suboxide growth. On the other hand, positive flat-band voltage (VOfb) shift was observed for the samples with the Si layer. The excessive VOfb, shift was relieved by increasing Si layer-thickness up to 2.0 nm. By using the 2.0-nm-thick Si passivation layer, superior p-MOSFET characteristics were obtained with little C-V hysteresis. This improvement would be attributed to reduction of oxide trap density by suppressing the Ge suboxide formation.