Effect of ultrathin Si passivation layer for Ge MOS structure with La 2O3 gate dielectric

J. Song; K. Kakushima; P. Ahmet; K. Tsutsui; N. Sugii; T. Hartori; H. Iwai

doi:10.1149/1.2981610

Effect of ultrathin Si passivation layer for Ge MOS structure with La ₂O₃ gate dielectric

J. Song^*, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hartori, H. Iwai

^*Corresponding author for this work

International College of Semiconductor Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The effect of ultrathin Si passivation layer on Ge MOS characteristics with La₂O₃ gate dielectric has been examined. Hysteresis on C-V curve was significantly reduced by inserting a Si passivation with thickness of over 1 nm due to suppression of Ge suboxide growth. On the other hand, positive flat-band voltage (VO_fb) shift was observed for the samples with the Si layer. The excessive VO_fb, shift was relieved by increasing Si layer-thickness up to 2.0 nm. By using the 2.0-nm-thick Si passivation layer, superior p-MOSFET characteristics were obtained with little C-V hysteresis. This improvement would be attributed to reduction of oxide trap density by suppressing the Ge suboxide formation.

Original language	English
Title of host publication	ECS Transactions - Physics and Technology of High-k Gate Dielectrics 6
Pages	285-293
Number of pages	9
Edition	5
DOIs	https://doi.org/10.1149/1.2981610
State	Published - 2008
Event	Physics and Technology of High-k Gate Dielectrics 6 - 214th ECS Meeting - Honolulu, HI, United States Duration: 13 Oct 2008 → 15 Oct 2008

Publication series

Name	ECS Transactions
Number	5
Volume	16
ISSN (Print)	1938-5862
ISSN (Electronic)	1938-6737

Conference

Conference	Physics and Technology of High-k Gate Dielectrics 6 - 214th ECS Meeting
Country	United States
City	Honolulu, HI
Period	13/10/08 → 15/10/08

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title = "Effect of ultrathin Si passivation layer for Ge MOS structure with La 2O3 gate dielectric",

abstract = "The effect of ultrathin Si passivation layer on Ge MOS characteristics with La2O3 gate dielectric has been examined. Hysteresis on C-V curve was significantly reduced by inserting a Si passivation with thickness of over 1 nm due to suppression of Ge suboxide growth. On the other hand, positive flat-band voltage (VOfb) shift was observed for the samples with the Si layer. The excessive VOfb, shift was relieved by increasing Si layer-thickness up to 2.0 nm. By using the 2.0-nm-thick Si passivation layer, superior p-MOSFET characteristics were obtained with little C-V hysteresis. This improvement would be attributed to reduction of oxide trap density by suppressing the Ge suboxide formation.",

author = "J. Song and K. Kakushima and P. Ahmet and K. Tsutsui and N. Sugii and T. Hartori and H. Iwai",

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series = "ECS Transactions",

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note = "null ; Conference date: 13-10-2008 Through 15-10-2008",

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Song, J, Kakushima, K, Ahmet, P, Tsutsui, K, Sugii, N, Hartori, T & Iwai, H 2008, Effect of ultrathin Si passivation layer for Ge MOS structure with La ₂O₃ gate dielectric. in ECS Transactions - Physics and Technology of High-k Gate Dielectrics 6. 5 edn, ECS Transactions, no. 5, vol. 16, pp. 285-293, Physics and Technology of High-k Gate Dielectrics 6 - 214th ECS Meeting, Honolulu, HI, United States, 13/10/08. https://doi.org/10.1149/1.2981610

Effect of ultrathin Si passivation layer for Ge MOS structure with La ₂O₃ gate dielectric. / Song, J.; Kakushima, K.; Ahmet, P.; Tsutsui, K.; Sugii, N.; Hartori, T.; Iwai, H.

ECS Transactions - Physics and Technology of High-k Gate Dielectrics 6. 5. ed. 2008. p. 285-293 (ECS Transactions; Vol. 16, No. 5).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Effect of ultrathin Si passivation layer for Ge MOS structure with La 2O3 gate dielectric

AU - Song, J.

AU - Kakushima, K.

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AU - Hartori, T.

AU - Iwai, H.

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N2 - The effect of ultrathin Si passivation layer on Ge MOS characteristics with La2O3 gate dielectric has been examined. Hysteresis on C-V curve was significantly reduced by inserting a Si passivation with thickness of over 1 nm due to suppression of Ge suboxide growth. On the other hand, positive flat-band voltage (VOfb) shift was observed for the samples with the Si layer. The excessive VOfb, shift was relieved by increasing Si layer-thickness up to 2.0 nm. By using the 2.0-nm-thick Si passivation layer, superior p-MOSFET characteristics were obtained with little C-V hysteresis. This improvement would be attributed to reduction of oxide trap density by suppressing the Ge suboxide formation.

AB - The effect of ultrathin Si passivation layer on Ge MOS characteristics with La2O3 gate dielectric has been examined. Hysteresis on C-V curve was significantly reduced by inserting a Si passivation with thickness of over 1 nm due to suppression of Ge suboxide growth. On the other hand, positive flat-band voltage (VOfb) shift was observed for the samples with the Si layer. The excessive VOfb, shift was relieved by increasing Si layer-thickness up to 2.0 nm. By using the 2.0-nm-thick Si passivation layer, superior p-MOSFET characteristics were obtained with little C-V hysteresis. This improvement would be attributed to reduction of oxide trap density by suppressing the Ge suboxide formation.

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