Effect of ultrathin Si passivation layer for Ge MOS structure with La 2O3 gate dielectric

J. Song*, K. Kakushima, P. Ahmet, K. Tsutsui, N. Sugii, T. Hartori, H. Iwai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The effect of ultrathin Si passivation layer on Ge MOS characteristics with La2O3 gate dielectric has been examined. Hysteresis on C-V curve was significantly reduced by inserting a Si passivation with thickness of over 1 nm due to suppression of Ge suboxide growth. On the other hand, positive flat-band voltage (VOfb) shift was observed for the samples with the Si layer. The excessive VOfb, shift was relieved by increasing Si layer-thickness up to 2.0 nm. By using the 2.0-nm-thick Si passivation layer, superior p-MOSFET characteristics were obtained with little C-V hysteresis. This improvement would be attributed to reduction of oxide trap density by suppressing the Ge suboxide formation.

Original languageEnglish
Title of host publicationECS Transactions - Physics and Technology of High-k Gate Dielectrics 6
Pages285-293
Number of pages9
Edition5
DOIs
StatePublished - 2008
EventPhysics and Technology of High-k Gate Dielectrics 6 - 214th ECS Meeting - Honolulu, HI, United States
Duration: 13 Oct 200815 Oct 2008

Publication series

NameECS Transactions
Number5
Volume16
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Conference

ConferencePhysics and Technology of High-k Gate Dielectrics 6 - 214th ECS Meeting
CountryUnited States
CityHonolulu, HI
Period13/10/0815/10/08

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