Effect of single grain boundary position on surrounding-gate polysilicon thin film transistors

Yiming Li*, Jung Y. Huang, Bo Shian Lee, Chih Hong Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

In this paper, single-grain-boundary-position-induced electrical characteristic variations in 300 nm surrounding-gate (i.e, gate-all-around, GAA) polysilicon thin film transistors (TFTs) are numerically investigated. For a 2T1C active-matrix circuit, a three-dimensional, device-circuit coupled mixed-mode simulation shows that the switching speed of GAA TFT can be improved by nine times, compared with the result of the circuit using single-gate (SG) polysilicon TFTs. The position of single grain boundary near the drain side has an ill effect on device performance, but the influence can be suppressed in the GAA polysilicon TFTs. We found that under the same threshold voltage, the variation of threshold voltage can be reduced from 15 % to 5 %, with varying of gate structures of the GAA polysilicon TFT.

Original languageEnglish
Title of host publication2007 7th IEEE International Conference on Nanotechnology - IEEE-NANO 2007, Proceedings
Pages1148-1151
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event2007 7th IEEE International Conference on Nanotechnology - IEEE-NANO 2007 - Hong Kong, China
Duration: 2 Aug 20075 Aug 2007

Publication series

Name2007 7th IEEE International Conference on Nanotechnology - IEEE-NANO 2007, Proceedings

Conference

Conference2007 7th IEEE International Conference on Nanotechnology - IEEE-NANO 2007
CountryChina
CityHong Kong
Period2/08/075/08/07

Keywords

  • Calibrated trap model parameters
  • Device-circuit mixed-mode simulation
  • Polysilicon TFT
  • Position of single grain boundary
  • Surrounding-gate

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