An efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of Analogto-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis.
|Number of pages||4|
|State||Published - 1 Jan 2001|
|Event||2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings - Hsinchu, Taiwan|
Duration: 18 Apr 2001 → 20 Apr 2001
|Conference||2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings|
|Period||18/04/01 → 20/04/01|