Dynamic voltage domain assignment technique for low power performance manageable cell based design

Elone Lee*, Feng Tso Chien, Ching Hwa Cheng, Jiun-In  Guo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Multi-voltage technique is an effective way to reduce power consumption. In the proposed voltage domain programmable (VDP) technique, high and low voltage domains applied to logic gates are programmable. The different voltage domains allow the chip performance and power consumption to be flexibly adjusted during circuit operation. In this proposed internal of the chip technique, the power switches possess the feature of flexible programming after chip manufacturing. The video decoder test chip proof of this novel methodology has 55% power reduction with good power-performance management mechanism.

Original languageEnglish
Title of host publication2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
Pages359-360
Number of pages2
DOIs
StatePublished - 28 Apr 2010
Event2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 - Taipei, Taiwan
Duration: 18 Jan 201021 Jan 2010

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010
CountryTaiwan
CityTaipei
Period18/01/1021/01/10

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  • Cite this

    Lee, E., Chien, F. T., Cheng, C. H., & Guo, J-I. (2010). Dynamic voltage domain assignment technique for low power performance manageable cell based design. In 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010 (pp. 359-360). [5419864] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2010.5419864