Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages

Nick Lindert*, Toshihiro Sugii, Stephen Tang, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalArticle

44 Scopus citations

Abstract

We have investigated circuit options to surpass the 1-V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use - from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed.

Original languageEnglish
Pages (from-to)85-89
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Volume34
Issue number1
DOIs
StatePublished - 1 Jan 1999

Keywords

  • Complementary pass-transistor logic
  • Dynamic threshold MOSFET
  • Low-power circuits
  • Regenerative pass-transistor logic
  • Supply voltage scaling

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