Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask

Hsin Chyh Hsu, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

NMOS with dummy-gate structure is proposed to significantly improve electrostatic discharge (ESD) robustness in a fully-salicided CMOS technology. By using this structure, ESD current is discharged far away from the salicided surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level. The HBM (MM) ESD robustness of the NMOS with dummy-gate structure (W/L = 480 /spl mu/m/0.18 /spl mu/m) has been successfully improved from 0.5 kV (125 V) to 1.5 kV (325 V) in a 130-nm fully-salicided CMOS process. Under the same layout area of the gate-grounded NMOS (ggNMOS), HBM (MM) ESD level can be improved over 300% (260%) by the proposed dummy-gate structure. The proposed dummy-gate structure is fully processed compatible to general salicided CMOS processes without additional mask, which is very cost-efficient for application in the IC products.

Original languageEnglish
Title of host publicationProceedings - 7th International Symposium on Quality Electronic Design, ISQED 2006
Pages503-506
Number of pages4
DOIs
StatePublished - 1 Dec 2006
Event7th International Symposium on Quality Electronic Design, ISQED 2006 - San Jose, CA, United States
Duration: 27 Mar 200629 Mar 2006

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference7th International Symposium on Quality Electronic Design, ISQED 2006
CountryUnited States
CitySan Jose, CA
Period27/03/0629/03/06

Fingerprint Dive into the research topics of 'Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask'. Together they form a unique fingerprint.

Cite this