Dual-section-average (DSA) analog-to-digital converter (ADC) in digital pulse width modulation (DPWM) DC-DC converter for reducing the problem of limiting cycle

Yu Chi Huang, Hsin Chao Chen, Tin Jong Tai, Ke-Horng Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

This paper proposes a dual-section average (DSA) analog-to-digital converter (ADC) to achieve a closed-loop digital pulse width modulation (DPWM) DC-DC converter with performance compatible to that by the analog PWM converter. For a 2.4V input voltage, a regulated output voltage of 1.2V can provide output current of 600mA without any off-chip compensators. Besides, the output ripple can be reduced to about 8mVp.p by theoretical result. The test chip was fabricated in 0.35μm CMOS technology. Owing to the parasitic resistance, the output ripple of the experimental result is within 8mVp.p. Furthermore, the transient recovery time is within 50μs when load current changes from 120mA to 600mA, or vice versa.

Original languageEnglish
Title of host publicationProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages145-148
Number of pages4
DOIs
StatePublished - 1 Dec 2008
Event2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
Duration: 3 Nov 20085 Nov 2008

Publication series

NameProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Conference

Conference2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
CountryJapan
CityFukuoka
Period3/11/085/11/08

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