Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism

Yu Tzu Tsai*, Cheng Chih Tsai, Cheng An Chien, Ching Hwa Cheng, Jiun-In  Guo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The high speed dual phase operation domino circuit, which includes high-performance and reliable characteristics is proposed, and the circuit design technique with practical implementation is presented. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64 bit high-speed multiplier with a built-in performance adjustment mechanism is successfully validated using TSMC 0.18 technology. The test chip shows x2.7 performance improvement compared to the conventional static CMOS logic design.

Original languageEnglish
Title of host publication2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
Pages85-86
Number of pages2
DOIs
StatePublished - 28 Mar 2011
Event2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011 - Yokohama, Japan
Duration: 25 Jan 201128 Jan 2011

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011
CountryJapan
CityYokohama
Period25/01/1128/01/11

Keywords

  • Domino circuit
  • Pipeline

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