Dual-alu crisc architecture and its compiling technique

Hong Chich Chou*, Chung-Ping Chung, Shyi Chyi Cheng

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


As semiconductor technology advances, more devices can be accommodated in a single VLSI chip. The feasibility of putting multifunctional units in a chip is then worth studying. Such an approach, however, will face software and hardware difficulties (and also tradeoffs). CRISC is a 32-bit single-chip VLSI processor architecture achieving high performance by means of RISC and multiple functional unit approaches. Dual-ALUs are used to execute instructions concurrently for fine-grained parallelism. Up to three instructions can be executed simultaneously by CRISC. Here, CRISC architecture design considerations and instruction cache scheme are investigated. Final microarchitecture and its incorporated software technique to produce object code for fine-grained parallel execution are described; its upper bound performance is estimated by an architectural model. A preliminary evaluation of the CRISC is also conducted, showing most satisfying results.

Original languageEnglish
Pages (from-to)297-312
Number of pages16
JournalComputers and Electrical Engineering
Issue number4
StatePublished - 1 Jan 1991

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