Drain Induced Barrier Lowering (DIBL) effect on the intrinsic capacitances of nano-scale MOSFETs

M. A. Karim*, Sriramkumar Venugopalan, Yogesh Singh Chauhan, Darsen Lu, Ali Niknejad, Chen-Ming Hu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

9 Scopus citations

Abstract

This paper presents a physical explanation of MOSFET intrinsic gate to drain capacitance (CCD) going negative due to Drain Induced Barrier Lowering (DIBL) effect. For the sub-90nm MOS devices, DIBL effect may be dominant enough to guide CGD to negative if de-embedded from parallel extrinsic overlap, outer and inner fringing capacitances. The possibility of this phenomenon is evident from the results of our 2-D TCAD simulations of conventional bulk MOS structure. However negative capacitances lead to non-convergence issue in circuit simulators and need to be bounded in MOS devices compact models.

Original languageEnglish
Title of host publicationTechnical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
Pages814-817
Number of pages4
StatePublished - 23 Nov 2011
EventNanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011 - Boston, MA, United States
Duration: 13 Jun 201116 Jun 2011

Publication series

NameTechnical Proceedings of the 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
Volume2

Conference

ConferenceNanotechnology 2011: Electronics, Devices, Fabrication, MEMS, Fluidics and Computational - 2011 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2011
CountryUnited States
CityBoston, MA
Period13/06/1116/06/11

Keywords

  • DIBL
  • MOSFET
  • Negative intrinsic capacitance

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