Management of process variation and random fluctuation is one of severe challenges in scaling down silicon-based devices continuously according to Moore's law. Emerging fluctuation sources  consists of the most critical random dopant fluctuation (RDF) which degrade device characteristic significantly. Unfortunately, recent studies on RDDs were reported for SOI FinFETs [1,5,8]. In this work, we for the first time statistically study characteristic fluctuation of 16-nm-gate high-/metal gate (HKMG) bulk FinFETs with different aspect ratios (AR = 1 and 2; AR = H fin/W fin) by random-discrete-dopants (RDDs) inside silicon fin channel, based upon our recent simulation studies [1-2,4-7]. Randomly generated devices with three-dimensional (3D) RDDs inside device channel is incorporated into quantum-mechanically corrected 3D device simulation. We compared the DC characteristics for planar and bulk FinFET devices. For the N-type bulk FinFET with AR = 2, it has higher I on and lower I off, further more the fluctuation of I on and I off are both smaller than the results of planar one, and the fluctuation of threshold voltage (σV th) is 46.2 mV for the simulated N-MOSFETs which is significantly reduced to 22.9 mV for the bulk FinFET with AR = 2. We also discuss drain induced barrier lowering (DIBL) and subthreshold swing (S.S) for all devices, and the AR2 FinFET possesses the best performance no matter for the DIBL or S.S effects. There is 68.7% improvement on DIBL and 30.1% improvement on S.S from the planar [1,5,7-8] to AR2 FinFET. The findings of this study indicate that there is a relation between DIBL and RDD's position in which they are near or away from the silicon fin channel surface. It explains the different fluctuation magnitudes of the degraded DIBL effect on devices with the same number of RDDs.