Downsizing of silicon MOSFETs beyond 0.1 μm

Hiroshi Iwai*

*Corresponding author for this work

Research output: Contribution to journalArticle

11 Scopus citations


This paper gives an overview of CMOS scaling in the range of sub-0.1 μm. Recent advance in the downsizing of MOSFETs by using various new techniques is described. Possible limitation and of MOSFET downsizing is predicted. A future concept of silicon LSIs in the 2010s is discussed.

Original languageEnglish
Pages (from-to)671-678
Number of pages8
JournalMicroelectronics Journal
Issue number10
StatePublished - Oct 1998


  • CMOS scaling
  • MOSFET downsizing
  • Silicon LSIs

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