Double snapback characteristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design

Ming-Dou Ker*, Kun Hsien Lin

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

35 Scopus citations

Abstract

The double snapback characteristic in the high-voltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.

Original languageEnglish
Pages (from-to)640-642
Number of pages3
JournalIEEE Electron Device Letters
Volume25
Issue number9
DOIs
StatePublished - 1 Sep 2004

Fingerprint Dive into the research topics of 'Double snapback characteristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design'. Together they form a unique fingerprint.

Cite this