A novel ΔΣ analogue-to-digital (ADC) architecture is proposed for second-order noise shaping enhancement. The new architecture is less dependent on the opamp DC gain than the earlier ΔΣ ADC with second-order noise shaping enhancement. Also, the proposed architecture reduces the complexity of the clock generator and zero optimisation compared to the earlier one. A ΔΣ ADC using the new configuration was designed and simulated. The results verify the advantages of the proposed structure.