Double-metal-gate nanocrystalline Si thin film transistors with flexible threshold voltage controllability

Uio Pu Chiou; Jia Min Shieh; Chih Chao Yang; Wen Hsien Huang; Yo Tsung Kao; Fu-Ming Pan

doi:10.1063/1.4832072

Double-metal-gate nanocrystalline Si thin film transistors with flexible threshold voltage controllability

Uio Pu Chiou, Jia Min Shieh, Chih Chao Yang, Wen Hsien Huang, Yo Tsung Kao, Fu-Ming Pan

Department of Materials Science and Engineering

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

We fabricated nano-crystalline Si (nc-Si:H) thin-film transistors (TFTs) with a double-metal-gate structure, which showed a high electron-mobility (μ_FE) and adjustable threshold voltages (V_th). The nc-Si:H channel and source/drain (S/D) of the multilayered TFT were deposited at 375°C by inductively coupled plasma chemical vapor deposition. The low grain-boundary defect density of the channel layer is responsible for the high μ_FE of 370 cm²/V-s, a steep subthreshold slope of 90 mV/decade, and a low V_th of -0.64 V. When biased with the double-gate driving mode, the device shows a tunable V_th value extending from -1 V up to 2.7 V.

Original language	English
Article number	203501
Journal	Applied Physics Letters
Volume	103
Issue number	20
DOIs	https://doi.org/10.1063/1.4832072
State	Published - 11 Nov 2013

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title = "Double-metal-gate nanocrystalline Si thin film transistors with flexible threshold voltage controllability",

abstract = "We fabricated nano-crystalline Si (nc-Si:H) thin-film transistors (TFTs) with a double-metal-gate structure, which showed a high electron-mobility (μFE) and adjustable threshold voltages (Vth). The nc-Si:H channel and source/drain (S/D) of the multilayered TFT were deposited at 375°C by inductively coupled plasma chemical vapor deposition. The low grain-boundary defect density of the channel layer is responsible for the high μFE of 370 cm2/V-s, a steep subthreshold slope of 90 mV/decade, and a low Vth of -0.64 V. When biased with the double-gate driving mode, the device shows a tunable Vth value extending from -1 V up to 2.7 V.",

author = "Chiou, {Uio Pu} and Shieh, {Jia Min} and Yang, {Chih Chao} and Huang, {Wen Hsien} and Kao, {Yo Tsung} and Fu-Ming Pan",

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doi = "10.1063/1.4832072",

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T1 - Double-metal-gate nanocrystalline Si thin film transistors with flexible threshold voltage controllability

AU - Chiou, Uio Pu

AU - Shieh, Jia Min

AU - Yang, Chih Chao

AU - Huang, Wen Hsien

AU - Kao, Yo Tsung

AU - Pan, Fu-Ming

PY - 2013/11/11

Y1 - 2013/11/11

N2 - We fabricated nano-crystalline Si (nc-Si:H) thin-film transistors (TFTs) with a double-metal-gate structure, which showed a high electron-mobility (μFE) and adjustable threshold voltages (Vth). The nc-Si:H channel and source/drain (S/D) of the multilayered TFT were deposited at 375°C by inductively coupled plasma chemical vapor deposition. The low grain-boundary defect density of the channel layer is responsible for the high μFE of 370 cm2/V-s, a steep subthreshold slope of 90 mV/decade, and a low Vth of -0.64 V. When biased with the double-gate driving mode, the device shows a tunable Vth value extending from -1 V up to 2.7 V.

AB - We fabricated nano-crystalline Si (nc-Si:H) thin-film transistors (TFTs) with a double-metal-gate structure, which showed a high electron-mobility (μFE) and adjustable threshold voltages (Vth). The nc-Si:H channel and source/drain (S/D) of the multilayered TFT were deposited at 375°C by inductively coupled plasma chemical vapor deposition. The low grain-boundary defect density of the channel layer is responsible for the high μFE of 370 cm2/V-s, a steep subthreshold slope of 90 mV/decade, and a low Vth of -0.64 V. When biased with the double-gate driving mode, the device shows a tunable Vth value extending from -1 V up to 2.7 V.

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Double-metal-gate nanocrystalline Si thin film transistors with flexible threshold voltage controllability

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