In this paper, we have developed a new method for studying the disturb failure mechanisms caused by stress-induced leakage current (SILC) in source-side erased flash memories. This method is able to directly separate the individual contributions of carrier charging/discharging in the oxide and the trap-assisted electron tunneling into the floating gate on the threshold voltage shift by using one memory cell only. Result shows that, at low oxide field, the disturb is mainly contributed by the carrier charging/discharging in the oxide. The disturb caused by carrier charging/discharging is due to the capacitance coupling effect instead of the flat-band voltage shift. While at high field, the trap-assisted electron tunneling induced floating-gate charge variation is the major factor of disturb failure.
|Number of pages||4|
|Journal||International Symposium on VLSI Technology, Systems, and Applications, Proceedings|
|State||Published - 1 Jan 1999|
|Event||Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan|
Duration: 7 Jun 1999 → 10 Jun 1999