Disturb-free Independently-controlled-Gate 7T FinFET SRAM cell

Yin Nien Chen*, Chien Yu Hsieh, Ming Long Fan, Vita Pi Ho Hu, Pin Su, Ching Te Chuang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We propose a novel Independently-controlled-Gate (IG) 7T FinFET SRAM cell. The cell utilizes the stacking-like property of split-gate super-high-V T FinFET devices to eliminate Read disturb and Half-Select disturb, and keeper and VSS-control to mitigate Read bit-line leakage. The stability and performance of the proposed cell are compared with the conventional 6T tied-gate cell and recently reported 6T-Column-Decoupled cell using TCAD mixed-mode simulations. 3D atomistic mixed-mode Monte-Carlo simulations are performed to investigate the impact of local random variations due to Fin LER. The results indicate that the proposed cell shows better cell stability and provides sufficient margins even considering intrinsic device variations.

Original languageEnglish
Title of host publicationProceedings of 2011 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2011
Pages34-37
Number of pages4
DOIs
StatePublished - 11 Jul 2011
Event2011 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2011 - Hsinchu, Taiwan
Duration: 25 Apr 201127 Apr 2011

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings

Conference

Conference2011 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2011
CountryTaiwan
CityHsinchu
Period25/04/1127/04/11

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